1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device having a sense amplifier for amplifying a potential difference occurring in a pair of bit lines.
2. Description of Related Art
A semiconductor memory device such as DRAM (Dynamic Random Access Memory) employs a sense amplifier for amplifying slight data read from memory cells to bit lines. The sense amplifier typically has a flip-flop circuit structure, in which one of a pair of bit lines at a high potential side is driven via a high-potential side common source line and the other at a low potential side is driven via a low-potential side common source line.
Since when the semiconductor memory device performs a read operation, many sense amplifiers are activated at the same time, there are problems that the potentials of the common source lines vary and a sense sensitivity and a sense speed lower. In order to solve the problems, there may be employed a system for overdriving the high-potential side common source line to a higher potential early in a sense operation (see Japanese Patent Application Laid-Open No. H10-242815). In the semiconductor memory described in Japanese Patent Application Laid-Open No. H10-242815, the common source line is overdriven to an external power supply potential early in the sense operation, thereby reducing a potential drop in the common source line.
The semiconductor memory described in Japanese Patent Application Laid-Open No. H10-242815 employs a delay circuit depending on a level of an internal power supply potential VINT and a delay circuit depending on a level of an external power supply potential VCC thereby to define a start timing of an overdrive period by an output of the former delay circuit and to define an end timing of the overdrive period by an output of the latter delay circuit. Thereby, the overdrive period is decided by a difference between the delay amount of the former delay circuit and the delay amount of the latter delay circuit.
However, since the internal power supply potential level is stabilized, the start timing of the overdrive period is substantially fixed. This means that a length of the overdrive period directly reflects the external power supply potential level, and thus there occurs a problem that the variation amount of the overdrive period depending on the external power supply potential level is too much. Since the overdrive period needs to be designed at an optimum value depending on the external power supply potential level, when the variation amount of the overdrive period is too much, a parameter with a large variation (the overdrive period) needs to match with a parameter with a large variation (the external power supply potential level) and thus the circuit is so difficult to be designed.